دانلود A Novel High-Speed Low-Power Binary Signed-Digit Adder

Abstract

Addition  is  one  of  the most  important  arithmetic operations in digital computation. Optimization of adders’ speed, power,  and  area  is  a  challenging  task.    To  this  end,  redundant number  system  has  been  proposed  in  the  literatures.  In  this  paper,  we  propose  a  new  redundant  binary  signed-digit  adder that  not  only  utilizes  specific  encoding  for  the  input  operands,  but also uses a new efficient adder structure. Using this technique  we  can  generate  low  power  signed  digit  adders  that  perform fast  additions. The  comparisons show delay, power and area reduction both on FPGA and Synopsys Design Vision tool.